The disclosure relates generally to integrated circuits (ICs), and, more particularly, to the fabrication of an interconnect structure with a noble metal cap and recessed dielectric adjacent such noble metal cap.
Electromigration (EM) has long been identified as the major metal failure mechanism. It is a reliability concern for Very Large Scale Integration (VLSI) circuits and manufacturing. EM not only needs to be overcome during process development period in order to qualify the process, but EM also persists through the lift time of the chip. Voids are created inside metal conductors due to metal ion movement caused by high density current flow. Although the fast diffusion path in copper (Cu) interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that Cu atom transport along the Cu/post-Chemical Mechanical Polish (CMP) dielectric cap interface plays an important role on EM lifetime projection. More specifically, the EM initiated voids nucleate at the Cu/dielectric cap interface and grow towards the bottom of the interconnect, which eventually results in a dead circuit open. It has been demonstrated that replacing Cu/dielectric cap interface with Cu/metal interface can enhance EM resistance. Observed electrical leakage related yield degradation, however, has delayed implementation of the Cu/metal interface.